Certain nonvolatile memory devices (e.g. NAND flash) exhibit endurance limitations where repeated erasure and writing will ultimately render a memory location (e.g. an addressed “block”) unusable. For example, a single level cell (SLC) NAND flash device block may become unusable after 100,000 erase-write cycles; a multi-level-cell (MLC) NAND Flash device block may reach its end-of-life in less than 10,000 cycles.
Numerous schemes have been developed to evenly distribute the actual physical location of write-erasures to extend the useful life of the device/system. These approaches and the algorithms behind them are called “wear leveling”. Mostly these approaches are based upon certain data regions not changing often (like software code stored on a hard disk) and reusing the memory locations associated with infrequently changing data for frequently changing data.